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SWCS049B 数据表(PDF) 85 Page - Texas Instruments |
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SWCS049B 数据表(HTML) 85 Page - Texas Instruments |
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85 / 119 page  85 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 www.ti.com SWCS049Q – JUNE 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Table 6-56. DEVCTRL_REG (continued) Type RW 7 6 5 4 3 2 1 0 PWR_OFF_ SEQ RTC_PWDN CK32K_CTRL SR_CTL_I2C_ SEL DEV_OFF_ RST DEV_ON DEV_SLP DEV_OFF Bits Field Name Description Type Reset 7 PWR_OFF_SEQ When 1, power-off will be sequential, reverse of power-on sequence (first resource to power on will be the last to power off). When 0, all resources disabled at the same time RW 0 6 RTC_PWDN When 1, disable the RTC digital domain (clock gating and reset of RTC registers and logic). This register bit is not reset in BACKUP state. RW 0 5 CK32K_CTRL Internal 32-kHz clock source control bit (EEPROM bit): when 0, the internal 32-kHz clock source is the crystal oscillator or an external 32-kHz clock in case the crystal oscillator is used in bypass mode when 1, the internal 32-kHz clock source is the RC oscillator. RW 0 4 SR_CTL_I2C_SEL Voltage scaling registers access control bit: when 0: access to registers by voltage scaling I2C when 1: access to registers by control I2C. The voltage scaling registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG, VDD2_SR_REG, VDDCtrl_OP_REG, and VDDCtrl_SR_REG. RW 1 3 DEV_OFF_RST Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event) and activate reset of the digital core. This bit is cleared in OFF state. RW 0 2 DEV_ON Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if DEV_OFF = 0 and DEV_OFF_RST = 0). EEPROM bit (Default value: See boot configuration) RW 0 1 DEV_SLP Write 1 allows SLEEP device state (if DEV_OFF = 0 and DEV_OFF_RST = 0). Write 0 will start an SLEEP-to-ACTIVE device state transition (wake-up event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in OFF state. RW 0 0 DEV_OFF Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event). This bit is cleared in OFF state. RW 0 Table 6-57. DEVCTRL2_REG Address Offset 0x40 Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description Device control register TSLOT_LENGTH: TURN OFF RESET Type RW 7 6 5 4 3 2 1 0 Reserved DCDC_SLEEP _LVL TSLOT_LENGTH SLEEPSIG_ POL PWON_LP_ OFF PWON_LP_ RST IT_POL Bits Field Name Description Type Reset 7 Reserved RO R returns 0s 0 6 DCDC_SLEEP_LVL When 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to be other than 0 V. When 0, no effect RW 0 |
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