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SWCS049B 数据表(PDF) 84 Page - Texas Instruments |
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SWCS049B 数据表(HTML) 84 Page - Texas Instruments |
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84 / 119 page  84 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 SWCS049Q – JUNE 2010 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Table 6-54. BBCH_REG (continued) Type RW 7 6 5 4 3 2 1 0 Reserved BBSEL BBCHEN Bits Field Name Description Type Reset 7:3 Reserved Reserved bit RO R returns 0s 0x00 2:1 BBSEL Back up battery charge voltage selection: BBSEL[1:0] = 00: 3.0 V BBSEL[1:0] = 01: 2.52 V BBSEL[1:0] = 10: 3.15 V BBSEL[1:0] = 11: VBAT RW 0x0 0 BBCHEN Back up battery charge enable RW 0 Table 6-55. DCDCCTRL_REG Address Offset 0x3E Physical Address Instance RESET DOMAIN: bits [7:3]: TURNOFF OFF RESET bits [2:0]: GENERAL RESET Description DCDC control register Type RW 7 6 5 4 3 2 1 0 Reserved TRACK VDD2_PSKIP VDD1_PSKIP VIO_PSKIP DCDCCKEXT DCDCCKSYNC Bits Field Name Description Type Reset 7 Reserved Reserved bit RO R returns 0s 0 6 TRACK 1: Tracking mode: LDO4 output follows VDD1 setting when VDD1 active. See Section 6.3.3.14 for more information. RW 0 0: Normal LDO operation without tracking 5 VDD2_PSKIP VDD2 pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 4 VDD1_PSKIP VDD1 pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 3 VIO_PSKIP VIO pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 2 DCDCCKEXT This signal control the muxing of the GPIO2 pad: When 0: this pad is a GPIO When 1: this pad is used as input for an external clock used for the synchronisation of the DCDCs RW 0 1:0 DCDCCKSYNC DCDC clock configuration: DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks DCDCCKSYNC[1:0] = 11: DCDC synchronous clock RW 0x1 Table 6-56. DEVCTRL_REG Address Offset 0x3F Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description Device control register Bit 0,1, and 3 : TURN OFF RESET |
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