YMF754-R datasheet(54/60 Pages) YAMAHA

54 / 60 page

YMF754

June 28, 1999

-54-

4-3. PCI Interface

(Fig.3, 4)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

PCICLK Cycle Time

tPCYC

PCICLK High Time

tPHIGH

PCICLK Low Time

tPLOW

PCICLK Slew Rate

V/ns

tPVAL

(Bused signal)

PCICLK to Signal Valid Delay

tPVAL(PTP) (Point to Point)

Float to Active Delay

tPON

Active to Float Delay

tPOFF

tPSU

(Bused signal)

*11 (Point to Point)

Input Setup Time to PCICLK

tPSU(PTP)

*12 (Point to Point)

Input Hold Time for PCICLK

tPH

Note : Top = 0-70°C, PVDD=3.3

±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V, C

L=10 pF

*11: This characteristic is applicable to REQ# and PCREQ# signal.

*12: This characteristic is applicable to GNT# and PCGNT# signal.

PCICLK

PCYC

PHIGH

0.3 VDD3

0.4 VDD3

0.5 VDD3

PLOW

Fig.3: PCI Clock timing

PCICLK

OUTPUT

INPUT

Tri-State

OUTPUT

1.5 V

PVAL

PON

POFF

PSU

Fig.4: PCI Bus Signals timing

YMF754-R 数据表(PDF) 54 Page - YAMAHA CORPORATION

YMF754-R 数据表(HTML) 54 Page - YAMAHA CORPORATION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载