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LP3907TL-PLNTO/NOPB 数据表(PDF) 22 Page - Texas Instruments |
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LP3907TL-PLNTO/NOPB 数据表(HTML) 22 Page - Texas Instruments |
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22 / 58 page  EN_T Vout Buck1 Vout Buck2 Vout LDO1 Vout LDO2 t1 t2 t3 t4 EN_T Vout Buck1 Vout Buck2 Vout LDO1 Vout LDO2 t2 t3 t4 t1 I 2 C Ext_Enable Pins Regulator ON Start Programmed Timing Sequence 0 1 EN_T 22 LP3907 SNVS511S – JUNE 2007 – REVISED APRIL 2016 www.ti.com Product Folder Links: LP3907 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Feature Description (continued) Figure 32. Power Rail Enable Logic Figure 33. LP3907 Default Power-Up Sequence Table 5. Power-On Timing Specification DESCRIPTION MIN NOM TYP UNIT t1 Programmable delay from EN_T assertion to VCC_Buck1 On 1.5 ms t2 Programmable delay from EN_T assertion to VCC_Buck2 On 2 ms t3 Programmable delay from EN_T assertion to VCC_LDO1 On 3 ms t4 Programmable delay from EN_T assertion to VCC_LDO2 On 6 ms Figure 34. LP3907 Default Power-Off Sequence |
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