LP3907TL-PLNTOSLASHNOPB datasheet(27/58 Pages) TI1

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C_SDA

C_SCL

START condition

STO

P condition

C_SCL

C_SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

LP3907

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SNVS511S – JUNE 2007 – REVISED APRIL 2016

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8.5 Programming

8.5.1 I2C-Compatible Serial Interface

8.5.1.1 I2C Signals

The LP3907features an I2C-compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock and

data respectively. Both signals need a pullup resistor according to the I2C specification. The LP3907 interface is

an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400kbit/s. See I2C

specification from NXP Semiconductors for further details.

8.5.1.2 I2C Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL); for example, the state

of the data line can only be changed when CLK is LOW.

Figure 39. I2C Signals: Data Validity

8.5.1.3 I2C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The 2C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 40. Start and Stop Conditions

8.5.1.4 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been

addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W).

LP3907TL-PLNTO/NOPB 数据表(PDF) 27 Page - Texas Instruments

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LP3907TL-PLNTO/NOPB 数据表(PDF) 27 Page - Texas Instruments

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