LP3907TL-PLNTOSLASHNOPB datasheet(44/58 Pages) TI1

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Vpp-rms =

Vpp-c

2 + V

pp-esr

Iripple

4 x f x C

Vpp-c =

LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

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9.2.2.2.5

Output Capacitor Selection for SW1, SW2

A 10-

μF, 6.3-V ceramic capacitor must be used on the output of the SW1 and SW2 magnetic DC-DC converters.

The output capacitor must be mounted as close to the output of the device as possible. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer, and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these

functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

(9)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

VPP–ESR = 2 × IRIPPLE × RESR

(10)

Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

(11)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent.

Calculate the RESR with the applicable switching frequency and ambient temperature.

Table 9. Suggested Capacitor Values

CAPACITOR

MIN VALUE (µF)

DESCRIPTION

RECOMMENDED TYPE

CLDO1

0.47

LDO1 output capacitor

Ceramic, 6.3 V, X5R

CLDO2

0.47

LDO2 output capacitor

Ceramic, 6.3 V, X5R

CSW1

SW1 output capacitor

Ceramic, 6.3 V, X5R

CSW2

SW2 output capacitor

Ceramic, 6.3 V, X5R

9.2.2.2.6

2C Pullup Resistor

Both SDA and SCL pins must have pullup resistors connected to VINLDO12 or to the power supply of the I2C

master. The values of the pullup resistors (typical approximately 1.8 k

Ω) are determined by the capacitance of

the bus. A resistor that is too large, combined with a given bus capacitance, results in a rise time that would

violate the maximum rise time specification. A too-small resistor results in a contention with the pulldown

transistor on either slave(s) or master.

9.2.2.3 Operation Without I2C Interface

Operation of the LP3907 without the I2C interface is possible if the system can operate with default values for the

LDO and Buck regulators (see Factory Programmable Options.) The I2C-less system must rely on the correct

default output values of the LDO and Buck converters.

9.2.2.3.1

High VIN High-Load Operation

Additional information is provided when the IC is operated at extremes of VIN and regulator loads. These are

described in terms of the Junction temperature and, Buck output ripple management.

9.2.2.3.2

Junction Temperature

The maximum junction temperature TJ-MAX-OP of 125°C of the device package Equation 12 through Equation 17

demonstrate junction temperature determination, ambient temperature TA-MAX, and total chip power must be

controlled to keep TJ below this maximum:

LP3907TL-PLNTO/NOPB 数据表(PDF) 44 Page - Texas Instruments

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LP3907TL-PLNTO/NOPB 数据表(PDF) 44 Page - Texas Instruments

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