LP3907TL-PLNTOSLASHNOPB datasheet(24/58 Pages) TI1

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EN1

nPOR

RDY1

EN2

RDY2

Counter

delay

Counter

delay

LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

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Figure 35 shows the simplest application of the POR, where both switcher enables are tied together. In Case 1,

EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does

not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice versa

scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the POR, where both switcher enables are tied together. Even if RDY1

ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before

going HIGH, as explained below.

Figure 36. Faults Occurring in Counter Delay After Start-Up

Figure 36 details the power good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2

are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:

COMPARATOR LEVEL

BUCK SUPPLY LEVEL

HIGH

Greater than 94%

LOW

Less than 85%

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also

works for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50

μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this

interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

LP3907TL-PLNTO/NOPB 数据表(PDF) 24 Page - Texas Instruments

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