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LP3907TL-PLNTO/NOPB 数据表(PDF) 30 Page - Texas Instruments |
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LP3907TL-PLNTO/NOPB 数据表(HTML) 30 Page - Texas Instruments |
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30 / 58 page ![]() 30 LP3907 SNVS511S – JUNE 2007 – REVISED APRIL 2016 www.ti.com Product Folder Links: LP3907 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated 8.6 Register Maps 8.6.1 LP3907 Control Registers REGISTER ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION 0x02 ICRA R Interrupt Status Register A 0x07 SCR1 R/W System Control 1 Register 0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register 0x11 BKLDOSR R Buck and LDO Output Voltage Status Register 0x20 VCCR R/W Voltage Change Control Register 1 0x23 B1TV1 R/W Buck1 Target Voltage 1 Register 0x24 B1TV2 R/W Buck1 Target Voltage 2 Register 0x25 B1RC R/W Buck1 Ramp Control 0x29 B2TV1 R/W Buck2 Target Voltage 1 Register 0x2A B2TV2 R/W Buck2 Target Voltage 2 Register 0x2B B2RC R/W Buck2 Ramp Control 0x38 BFCR R/W Buck Function Register 0x39 LDO1VCR R/W LDO1 Voltage Control Registers 0x3A LDO2VCR R/W LDO2 Voltage Control Registers 8.6.1.1 Interrupt Status Register (ISRA) 0x02 This register informs the System Engineer of the temperature status of the chip. D7-D2 D1 D0 Name — Temp 125°C — Access — R — Data Reserved Status bit for thermal warning PMIC T>125°C 0 – PMIC Temp. < 125°C 1 – PMIC Temp. > 125°C Reserved Reset 0 0 0 8.6.1.2 Control 1 Register (SCR1) 0x07 This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode for the bucks, and also to select between an internal and external clock for the bucks. D7 D6-D4 D3 D2 D1 D0 Name — EN_DLY — FPWM2 FPWM1 ECEN Access — R/W — R/W R/W R/W Data Reserved Selects the preset delay sequence from EN_T assertion (shown below) Reserved Buck2 PWM /PFM Mode select 0 – Auto Switch PFM - PWM operation 1 – PWM Mode Only Buck 1 PWM /PFM Mode select 0 – Auto Switch PFM - PWM operation 1 – PWM Mode Only Reserved Reset 0 Factory-Programmed Default 1 Factory-Programmed Default Factory-Programmed Default 0 |
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