MCP23017-ESLASHML datasheet(20/42 Pages) MICROCHIP

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MCP23017/MCP23S17

DS20001952C-page 20

 2005-2016 Microchip Technology Inc.

3.5.5

INTERRUPT CONTROL REGISTER

The INTCON register controls how the associated pin

value is compared for the interrupt-on-change feature.

If a bit is set, the corresponding I/O pin is compared

against the associated bit in the DEFVAL register. If a

bit value is clear, the corresponding I/O pin is compared

against the previous value.

3.5.6

CONFIGURATION REGISTER

The

IOCON

contains

several

bits

for

configuring the device:

The BANK bit changes how the registers are mapped

(see Tables 3-4 and3-5 for more details).

• If BANK = 1, the registers associated with each

port are segregated. Registers associated with

PORTA are mapped from address 00h - 0Ah and

registers associated with PORTB are mapped

from 10h - 1Ah.

• If BANK = 0, the A/B registers are paired. For

example, IODIRA is mapped to address 00h and

IODIRB is mapped to the next address (address

01h). The mapping for all registers is from 00h

-15h.

It is important to take care when changing the BANK bit

as the address mapping changes after the byte is

clocked into the device. The address pointer may point

to an invalid location after the bit is modified.

For

example,

the

device

configured

automatically increment its internal Address Pointer,

the following scenario would occur:

• BANK = 0

• Write 80h to address 0Ah (IOCON) to set the

BANK bit

• Once the write completes, the internal address

now points to 0Bh which is an invalid address

when the BANK bit is set.

For this reason, when changing the BANK bit, it is

advised to only perform byte writes to this register.

The MIRROR bit controls how the INTA and INTB pins

function with respect to each other.

• When MIRROR = 1, the INTn pins are functionally

OR’ed so that an interrupt on either port will cause

both pins to activate.

• When MIRROR = 0, the INT pins are separated.

Interrupt conditions on a port will cause its

respective INT pin to activate.

The Sequential Operation (SEQOP) controls the

incrementing function of the Address Pointer. If the

address pointer is disabled, the Address Pointer does

not automatically increment after each byte is clocked

during a serial transfer. This feature is useful when it is

desired to continuously poll (read) or modify (write) a

The Slew Rate (DISSLW) bit controls the slew rate

function on the SDA pin. If enabled, the SDA slew rate

will be controlled when driving from a high to low.

The

Hardware

Address

Enable

(HAEN)

bit

enables/disables

hardware

addressing

the

MCP23S17 only. The address pins (A2, A1 and A0)

must be externally biased, regardless of the HAEN bit

value.

If enabled (HAEN = 1), the device’s hardware address

matches the address pins.

If disabled (HAEN = 0), the device’s hardware address

is A2 = A1 = A0 = 0.

INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)

R/W-0

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

IOC<7:0>: Controls how the associated pin value is compared for interrupt-on-change <7:0>

= Pin value is compared against the associated bit in the DEFVAL register.

= Pin value is compared against the previous pin value.

Note 1:

Refer to INTCON and GPINTEN.

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