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MCP23017-E/ML 数据表(PDF) 9 Page - Microchip Technology |
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MCP23017-E/ML 数据表(HTML) 9 Page - Microchip Technology |
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9 / 42 page ![]() 2005-2016 Microchip Technology Inc. DS20001952C-page 9 MCP23017/MCP23S17 FIGURE 1-7: GPIO AND INT TIMING 5Data Hold Time THD 20 — — ns 1.8V – 5.5V 10 — — ns 2.7V – 5.5V 6CLK Rise Time TR —— 2 µs Note 1 7CLK Fall Time TF —— 2 µs Note 1 8Clock High Time THI 90 — — ns 1.8V – 5.5V 45 — — ns 2.7V – 5.5V 9 Clock Low Time TLO 90 — — ns 1.8V – 5.5V 45 — — ns 2.7V – 5.5V 10 Clock Delay Time TCLD 50 — — ns 11 Clock Enable Time TCLE 50 — — ns 12 Output Valid from Clock Low TV — — 90 ns 1.8V – 5.5V — — 45 ns 2.7V – 5.5V 13 Output Hold Time THO 0— — ns 14 Output Disable Time TDIS — — 100 ns TABLE 1-4: SPI INTERFACE REQUIREMENTS (CONTINUED) SPI Interface AC Characteristics: Unless otherwise noted, 1.8V V DD 5.5V at -40C TA +125C Param. No. Characteristic Sym. Min. Typ. Max. Units Conditions Note 1: This parameter is characterized, not 100% tested. 50 SCL/SCK SDA/SI In GPn Pin D0 D1 LSb of data byte zero during a write or read INT Pin INT Pin Active 51 command, depending on parameter Output GPn Pin Input Inactive 53 52 Register Loaded |
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