LMX2430 datasheet(36/49 Pages) NSC

36 / 49 page

1.0 Functional Description (Continued)

1.8.3 Digital Filtered Lock Detect Output

A digital filtered lock detect status generated from the phase

detector is also available on the Ftest/LD output pin if se-

lected. The lock detect digital filter compares the difference

bewteen the phases of the inputs to the PFD to an RC

generated delay of approximately 15 ns. If the phase error is

less than the 15 ns RC delay for 5 consecutive reference

cycles, the PLL enters a locked state (HIGH). Once in lock,

the RC delay is changed to approximately 30 ns. Once the

phase error becomes greater than the 30 ns RC delay, the

PLL falls out of lock (LOW). When the PLL is in powerdown

mode, the Ftest/LD output is forced LOW. A flow chart of the

digital filtered lock detect output is shown below.

20053503

Similarly, three separate digital filtered lock detect signals

are routed to the multiplexer. Two of these monitor the lock

status of the individual synthesizers. The third detects the

condition when both the RF and IF synthesizers are in a

locked state. External circuitry is not required when the

digital filtered lock detect option is selected. Refer to Section

2.10 for details on how to program the different digital filtered

lock detect options.

LMX2430 数据表(PDF) 36 Page - National Semiconductor (TI)