2.0 Programming Description

2.1 MICROWIRE INTERFACE

The 24-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 21-bit DATA[20:0] FIELD and a

3-bit ADDRESS[2:0] FIELD as shown below. The ADDRESS FIELD is used to decode the internal control register address. When

LE transitions HIGH, DATA stored in the shift register is loaded into one of 6 control registers depending on the state of the

ADDRESS bits. The MSB of DATA is loaded into the shift register first. The DATA FIELD assignments are shown in Section 2.3

CONTROL REGISTER CONTENT MAP.

MSB

LSB

DATA[20:0]

ADDRESS[2:0]

23

3 2

0

2.2 CONTROL REGISTER LOCATION

The ADDRESS[2:0] bits decode the internal register address. The table below shows how the ADDRESS bits are mapped into

the target control register.

ADDRESS[2:0]

Target

FIELD

Register

00

0

R0

00

1

R1

01

0

R2

01

1

R3

10

0

R4

10

1

R5

2.3 CONTROL REGISTER CONTENT MAP

The control register content map describes how the bits within each control register are allocated to specific control functions. The

bits that are marked 0 should be programmed as such to ensure proper device operation.

Reg

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9876543210

DATA[20:0] FIELD

ADDRESS

[2:0]

FIELD

R0

MUX[3:2]

RF_

RST

RF_

CPT

RF_

CPG

RF_

CPP

RF_R[14:0]

0

0

0

R1

RF_

PD

RF_

P

LMX2430/33

RF_B[14:0]

LMX2430/33

RF_A[3:0]

001

R1

RF_

PD

RF_

P

LMX2434

RF_B[13:0]

LMX2434

RF_A[4:0]

001

R2

000000000

RF_TOC[11:0]

0

1

0

R3

MUX[1:0]

IF_

RST

IF_

CPT

IF_

CPG

IF_

CPP

IF_R[14:0]

0

1

1

R4

IF_

PD

IF_

P

0

IF_B[13:0]

IF_A[3:0]

1

0

0

R5

000000000

IF_TOC[11:0]

1

0

1

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