AP0101CS/D Rev. 7, 1/16 EN

5

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

System Interfaces

Figure 2:

Typical Configuration

Notes:

1. This typical configuration shows only one scenario out of multiple possible variations for this sen-

sor.

however, greater values may be used for slower transmission speed.

3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.

4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The

capacitors should be ceramic and need to have X5R or X7R dielectric.

5. TRST_BAR connects to GND for normal operation.

6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply

are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-

out and design consideration

S ensor IO

pow er

Host IO

pow er

EXTCLK_OUT

RESET_BAR_OUT

FV_IN

LV_IN

PIXCLK _IN

DIN [11:0]

TRIGGER_OUT

1.8V

(R egulator

IP )

1.2V (Regulator OP)

P ower up C ore and

PLL

GND_REG

FV_OUT

LV_OUT

PIXCLK_OUT

EXTCLK

XTAL

SPI_CS_BAR

SPI_CLK

SPI_SDO

SPI_SDI

GPIO_1

OT P M

Power

GND

2

2

GPIO_2

GPIO_3

GPIO_4

GPIO_5

FRAME_SYNC

STANDBY

Oscillator