AP0101CS datasheet(36/42 Pages) ONSEMI

36 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

Electrical Specifications

Figure 26:

Parallel Digital Output I/O Timing

Notes:

1. VIH/VIL restrictions apply.

2. This is applicable only a when the PLL is bypassed. When the PLL is being used then the user should

ensure that VIH/VIL is met.

Table 20:

AC Electrical Characteristics (Referring to Figure 26)

Default Setup Conditions: fEXTCLK= 27 MHz, fPIXCLK = 74.125 MHz or fPIXCLK = 84 MHz, VDDIO_H = VDD_OTPM = 2.8V,

VDD_REG = VDDIO_S = 1.8V, TA = 25°C unless otherwise stated

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Notes

fEXTCLK

External clock frequency

MHz

External input clock rise time

10%-90% VDDIO_H

–

External input clock fall time

90%-10% VDDIO_H

–

DEXTCLK External input clock duty cycle

tJITTER

External input clock jitter

–

500

–

fPIXCLK

Pixel clock frequency (one-clock/pixel)

74.25

MHz

Pixel clock frequency (two-clocks/pixel)

MHz

tRPIXCLK Pixel clock rise time (10 - 90%)

CLOAD=35pf

–

tFPIXCLK Pixel clock fall time (10 - 90%)

CLOAD=35pf

–

tPD

PIXCLK to data valid

–

tPFH

PIXCLK to FV HIGH

–

tPLH

PIXCLK to LV HIGH

–

tPFL

PIXCLK to FV LOW

–

tPLL

PIXCLK to LV LOW

–

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