AP0101CS datasheet(10/42 Pages) ONSEMI

10 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

System Interfaces

Note:

If the system cannot support this power supply slew rate, then power supplies must be designed

to overcome inrush currents in Table 24, “Inrush Current,” on page 38.

Reset

The AP0101CS has 3 types of reset available:

• A hard reset is issued by toggling the RESET_BAR signal

• A soft reset is issued by writing commands through the two-wire serial interface

• An internal power-on reset

Table 7 shows the output states when the part is in various states.

Table 6:

Power-Up and Power-Down Signal Timing

Symbol Parameter

Min

Typ

Max

Unit

Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM

–

Delay from VDDIO_H to VDD_REG

–

EXTCLK activation

t2 + 1

–

First serial command

100

–

EXTCLK cycles

EXTCLK cutoff

–

Delay from VDD_REG to VDDIO_H

–

Delay from VDDIO_S, VDDIO_OTPM to VDDIO_H

–

dv/dt

Power supply ramp time (slew rate)

–

0.1

V/s

Table 7:

Output States

Name

Hardware States

Firmware States

Notes

Reset State

Default State Hard Standby

Soft Standby

Streaming

Idle

EXTCLK

(clock

running or

stopped)

(clock

running)

(clock running

or stopped)

(clock

running)

(clock

running)

(clock

running)

Input

XTAL

n/a

Input

RESET_BAR

(asserted)

(negated)

Input

SCLK

n/a

(clock running

or stopped)

(clock running

or stopped)

(clock running

or stopped)

(clock running

or stopped)

Input. Must always

be driven to a valid

logic level

SDATA

High-

impedance

High-

impedance

High-

impedance

High-

impedance

High-

impedance

High-

impedance

Input/Output. A

valid logic level

should be

established by pull-

SADDR

n/a

Input. Must always

be driven to a valid

logic level

FRAME_SYNC

n/a

Input. Must always

be driven to a valid

logic level

STANDBY

n/a

(negated)

(asserted)

(negated)

Input. Must always

be driven to a valid

logic level

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