AP0101CS datasheet(39/42 Pages) ONSEMI

39 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

Two-Wire Serial Register Interface

The electrical characteristics of the slave two-wire serial register interface (SCLK,

SDATA) are shown in Figure 27 and Table 25.

Figure 27:

Slave Two-Wire Serial Bus Timing Parameters (CCIS)

Notes:

1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

2. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCLK signal.

4. Cb = total capacitance of one bus line in pF.

The electrical characteristics of the master two-wire serial register interface (M_SCLK,

M_SDATA) are shown in Figure 28 and Table 26.

Table 25:

Slave Two-Wire Serial Bus Characteristics (CCIS)

Default Setup Conditions: fEXTCLK = 27 MHz, fPIXCLK = 74.125 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S =

1.8V, Tj = 25°C unless otherwise stated

Parameter

Symbol

Standard-Mode

Fast-Mode

Unit

Min

Max

Min

Max

SCLK Clock Frequency

fSCL

100

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

tHD;STA

4.0

0.6

s

LOW period of the SCLK clock

tLOW

4.7

1.3

s

HIGH period of the SCLK clock

tHIGH

4.0

0.6

s

Set-up time for a repeated START condition

tSU;STA

4.7

0.6

s

Data hold time

tHD;DAT

3.453

00.93

s

Data set-up time

tSU;DAT

250

100

Rise time of both SDATA and SCLK signals

1000

20 + 0.1Cb4

300

Fall time of both SDATA and SCLK signals

300

20 + 0.1Cb4

300

Set-up time for STOP condition

tSU;STO

4.0

0.6

s

Bus free time between a STOP and START

condition

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

Serial interface input pin capacitance

CIN_SI

3.3

SDATA max load capacitance

CLOAD_SD

SDATA pull-up resistor

RSD

1.5

4.7

1.5

4.7

K

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDATA

SCLK

tBUF

tHD;STA

AP0101CS 数据表(PDF) 39 Page - ON Semiconductor

AP0101CS 数据表(HTML) 39 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载

链接网址

AP0101CS 数据表(PDF) 39 Page - ON Semiconductor

AP0101CS 数据表(HTML) 39 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表 下载

链接网址

数据表下载