AP0101CS datasheet(9/42 Pages) ONSEMI

9 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

System Interfaces

Power-Up and Down Sequence

Powering up and down the AP0101CS requires voltages to be applied in a particular

order, as seen in Figure 4. The timing requirements are shown in Table 6. The AP0101CS

includes a power-on reset feature that initiates a reset upon power up of the AP0101CS.

Figure 4:

Power-Up and Power-Down Sequence

Table 5:

Package Pinout

EXTCLK

XTAL

SCLK

SPI_SDO

DOUT[15]

DOUT[13]

DOUT[10]

DOUT[9]

DOUT[8]

VDD

VDDIO_H SDATA

SPI_SDI

DOUT[14]

DOUT[12]

DOUT[11]

DOUT[7]

DOUT[6]

EXT_CLK_OUT

VDDIO_S

SADDR

SPI_CS_BA

GND

PIXCLK_OUT FV_OUT

DOUT[5]

DOUT[4]

RESET_BAR_OUT VDD

GND

SPI_SCLK

GND

TRST_BAR

LV_OUT

DOUT[3]

DOUT[2]

DIN[3]

DIN[7]

GND

FB_SENSE

GND

VDD_PLL

DOUT[1]

DOUT[0]

DIN[11]

DIN[2]

LDO_OP

GND_REG

GND

VDD_PLL

VDDIO_OTPM

DIN[6]

DIN[1]

DIN[4]

VDD_REG

VDDIO_S

VDD

RESET_BAR

GPIO[4]

GPIO[5]

DIN[10]

DIN[0]

DIN[8]

FV_IN

M_SDATA

VDDIO_H

FRAME_SYNC GPIO[2]

GPIO[3]

DIN[5]

DIN[9]

PIXCLK_IN LV_IN

M_SCLK

VDD

STANDBY

TRIGGER_OUT GPIO[1]

VDDIO_H

VDD_REG

EXTCLK

SCLK

SDATA

VDDIO_S, VDDIO_OTPM

dv/dt

RESET

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