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TAS5036IPFCR 数据表(PDF) 9 Page - Texas Instruments |
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TAS5036IPFCR 数据表(HTML) 9 Page - Texas Instruments |
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9 / 49 page ![]() Introduction 4 SLES044B—November 2002 TAS5036 1.4 Ordering Information Texas Instruments T AS Audio Solutions 5036 C PAG Device Number Temperature Range Package Type AVAILABLE OPTIONS PACKAGE TA PLASTIC 80-PIN TQFP (PAG) 0 °C to 70°C TAS5036CPAG 1.5 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AVDD_OSC 80 P Analog power supply for internal oscillator cells AVDD_PLL 4 P Analog power supply for PLL AVSS_OSC 77 AO Analog ground for internal oscillator cells AVSS_PLL 7 P Analog ground for PLL CLIP 25 DO Digital clipping indicator, active low CS0 18 DI I2C serial control chip address select input, active high DBSPD 24 DI Sample rate is double speed (88.2 kHz or 96 kHz), active high DM_SEL1 36 DI De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none) DM_SEL2 35 DI De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz DVDD 32 P Digital power supply DVDD_PWM 57 P Digital power supply for PWM DVDD_RCL 59 P Digital power supply for reclocker DVSS 33, 76 P Digital ground for digital core and most of I/O buffers DVSS1 10, 38, 39 DIO Digital ground for digital core and most of I/O buffers DVSS_PWM 56 P Digital ground for PWM DVSS_RCL 58 P Digital ground for reclocker ERR_RCVRY 13 DI Error recovery input, active low LRCLK 31 DIO Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S = 1) M_S 37 DI Master/slave mode input signal (master = 1, slave = 0) MCLK_IN 3 DI MCLK input, slave mode (or master / double-speed mode) MCLK_OUT 29 DO MCLK output buffered system clock output if M_S = 1; otherwise set to 0 MUTE 14 DI Mute input signal, active low (muted signal = 0, normal mode = 1) N/C 1, 2, 8, 11, 19–23, 40 Not connected PDN 15 DI Power down, active low |
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