TAS5036IPFCR datasheet(19/49 Pages) TI

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Architecture Overview

SLES044B—November 2002

TAS5036

SCLK

24 Clks

LRCLK

Left Channel

MSB

LSB

2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)

NOTE: All data presented in 2s complement form with MSB first.

24 Clks

Right Channel

MSB

LSB

24-Bit Mode

20-Bit Mode

16-Bit Mode

Figure 2–8. Right-Justified 48-Fs Format

2.1.7.4

DSP Mode Timing

DSP mode timing uses an LRCLK to define when data is to be transmitted for both channels. A bit clock running

at 64

× Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following

the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036

masks unused trailing data bit positions.

SCLK

LRCLK

64 SCLKS

LSB

MSB

16 Bits

Left

Channel

16 Bits

Right

Channel

32 Bits Unused

SDIN

LSB

MSB

Figure 2–9. DSP Format

TAS5036IPFCR 数据表(PDF) 19 Page - Texas Instruments

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