TAS5036IPFCR datasheet(16/49 Pages) TI

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Architecture Overview

SLES044B—November 2002

TAS5036

Table 2–5. Supported Word Lengths

DATA MODES

WORD

LENGTHS

MOD2

MOD1

MOD0

Right justified, MSB first

I2S

Left justified, MSB first

DSP frame

2.1.7.1

I2S Timing

I2S timing uses an LRCLK to define when the data being transmitted is for the left channel or the right channel.

The LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs

is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state

to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit

clock. The TAS5036 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit

clock.

SCLK

32 Clks

LRCLK (Note Reversed Phase)

Left Channel

24-Bit Mode

20-Bit Mode

16-Bit Mode

MSB

LSB

SCLK

32 Clks

Right Channel

MSB

LSB

2-Channel I2S (Philips Format) Stereo Input

Figure 2–3. I2S 64-Fs Format

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