TAS5036IPFCR datasheet(24/49 Pages) TI

24 / 49 page

Architecture Overview

SLES044B—November 2002

TAS5036

–10

3.18 (50

µs)

10.6 (15

µs)

f – Frequency – kHz

De-Emphasis

Figure 2–11. De-Emphasis Filter Characteristics

2.4

Pulse Width Modulator (PWM)

The TAS5036 contains six channels of high performance digital Equibit PWM modulators that are designed

to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load)

configuration. The TAS5036 device uses noise shaping and sophisticated error correction algorithms to

achieve high power efficiency and high-performance digital audio reproduction.

The PWM provides six pseudo-differential outputs to drive six monolithic power stages (such as TAS5110)

or six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in

single-ended or bridged configurations. The TAS5036 also provides a high performance differential output that

can be used to drive an external analog headphone amplifier.

2.4.1 Clipping Indicator

The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum

allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.

2.4.2 Error Recovery

Error recovery is used to provide error management and to permit the PWM output to be reset while preserving

all inter-volume, inter-channel delay, dc offsets, and the other internal settings. Error recovery is initiated by

bringing the /ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit

in control register 1. Error recovery is a level sensitive signal.

The device also performs an error recovery automatically:

•

When the speed configuration is changed to normal, double, or quad speed

•

Following a change in the serial data bus interface configuration

When ERR_RCVRY is brought low, all valid signals go low, and the PWM-P and PWM-M outputs go low. If

there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is

brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization

sequence. After the initialization time, the TAS5036 begins normal operation. During error recovery, all

controls and device settings that were not updated are maintained in their current configurations.

To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between

the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay

can be selected to be either 6

µs or 47 µs.

During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error

recovery register bit is returned to normal operation state. Table 2–11 shows the device output signal states

while during error recovery.

TAS5036IPFCR 数据表(PDF) 24 Page - Texas Instruments

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