TAS5036IPFCR datasheet(18/49 Pages) TI

18 / 49 page

Architecture Overview

SLES044B—November 2002

TAS5036

SCLK

24 Clks

LRCLK

Left Channel

MSB

LSB

2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)

24 Clks

Right Channel

MSB

LSB

24-Bit Mode

Figure 2–6. Left-Justified 48-Fs Format

2.1.7.3

Right-Justified Timing

Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and

the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at

48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for

24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks the

LSB of data. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5036 masks

unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.

SCLK

32 Clks

LRCLK

Left Channel

24-Bit Mode

20-Bit Mode

16-Bit Mode

MSB

LSB

2-Channel Right-Justified (Sony Format) Stereo Input

NOTE: All data presented in 2s complement form with MSB first.

32 Clks

Right Channel

MSB

LSB

Figure 2–7. Right-Justified 64-Fs Format

TAS5036IPFCR 数据表(PDF) 18 Page - Texas Instruments

TAS5036IPFCR 数据表(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载