TAS5036IPFCR datasheet(25/49 Pages) TI

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Architecture Overview

SLES044B—November 2002

TAS5036

Table 2–11. Device Outputs During Error Recovery

SIGNAL

MODE

SIGNAL STATE

Valid 1–Valid 6

All

Low

PWM P-outputs

All

Low

PWM M-outputs

All

Low

MCLKOUT

All

Low

SCLK

Master

Low

SCLK

Slave

Signal input

LRCLK

Master

Low

LRCLK

Slave

Signal input

SDA

All

Signal input

CLIP

All

High

The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.

2.4.3 Individual Channel Error Recovery

Individual channel error recovery is used to provide error management and to permit the PWM output to be

turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery

While the error recover bits are brought low, the valid signals goes to the low state. When the error recovery

bits are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.

The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is

selectable. This delay can be selected to be either 6

µs or 47 µs.

The TAS5036 controls the relative timing of the pseudo-differential drive control signals plus the valid signal

to minimize the production of system noise during error recovery operations. The transitions to valid low and

valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.

2.4.4 PWM DC-Offset Correction

An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset

present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of

±1.56% of full scale. The default value is zero correction represented by 00 (hex). These values can be

changed at any time through the serial control interface.

2.4.5 Inter-Channel Delay

An 8-bit value can be programmed to each of the six PWM inter-channel delay registers to add a delay per

channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK

(or alternatively the external PLL clock frequency). Each subsequent channel has a default value that is N

DCLKs larger than the preceding channel. The default values are 0 for the first channel and 16 for each

successive channel.

These values can be updated upon power up through the serial control interface. This delay is generated in

the PWM block with the appropriate control signals generated in the CTL block.

These values can be changed at any time through the serial control interface. The optimum performance of

the TAS5036 can be achieved using an interchannel delay of 21.

2.4.6 ABD Delay

A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for

all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default values is 11 DCLK clock cycles

(01011). This value is mask programmable. These values can be changed at any time through the serial

control interface.

The optimum performance of the TAS5036 can be achieved with an ABD delay of 30.

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