TAS5036IPFCR datasheet(12/49 Pages) TI

12 / 49 page

Architecture Overview

SLES044B—November 2002

TAS5036

There are three data rates: normal speed, double speed, and quad speed.

Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the

master and slave modes. The PWM is placed in normal speed by setting the DBSPD terminal low or by setting

the normal mode bits in the system control register through the serial control interface. Following this

operation, the PWM performs an error recovery sequence automatically and operates in the normal speed

mode.

Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. Double speed is supported

in master and slave modes. The PWM is placed in double speed mode by setting the DBSPD terminal high

or by setting the double speed bits in the system control register through the serial control interface. Following

this operation, the PWM performs an error recovery sequence automatically and operates in the double speed

mode.

Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. Quad-speed mode is auto

detected supported in slave mode and invoked by control in master mode in slave mode. If the device is not

in double speed mode, quad-speed mode is automatically detected when MCLK_IN is 128Fs. In master mode,

the PWM is placed in quad-speed mode by setting the quad-speed bit in the system control register through

the serial control interface.

Table 2–1. Normal-Speed, Double-Speed, and Quad-Speed Operation

QUAD-SPEED CONTROL

DBSPD TERMINAL OR

CONTROL REGISTER BIT

MODE

SPEED SELECTION

Master or slave

Normal speed

Master or slave

Double speed

Master or slave

Quad speed

Slave

Quad speed if MCLK_IN = 128Fs

Master or slave

Error

2.1.2 Clock Master/Slave Mode (M_S)

Clock master and slave mode can be invoked using the M_S (master slave) terminal.

This terminal specifies the default mode that is set immediately following a device RESET. The serial data

interface setting permits the clock generation mode to be changed during normal operation.

The transition to master mode occurs:

•

Following a RESET when M_S terminal has a logic high applied

The transition to slave mode occurs:

•

Following a RESET when M_S terminal has a logic low applied

2.1.3 Clock Master Mode

When M_S = 1 following a RESET, the TAS5036 provides the master clock, SCLK, and LRCLK to the rest of

the system. In the master mode, the TAS5036 outputs the audio system clocks MCLK_OUT, SCLK, and

LRCLK.

The TAS5036 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).

The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or

a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN

is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample

rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK

frequency is the data sample rate.

2.1.3.1

Crystal Type and Circuit

In clock master mode the TAS5036 can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,

the TAS5036 uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5036 as

shown in Figure 2–1.

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