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ADRF6720-27ACPZ-R7 数据表(PDF) 30 Page - Analog Devices |
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ADRF6720-27ACPZ-R7 数据表(HTML) 30 Page - Analog Devices |
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30 / 44 page ![]() Data Sheet ADRF6720-27 Rev. B | Page 29 of 43 Figure 60. PFD Spurious Emissions on Modulator Output, fLO + N × fPFD; fLO = 1781.76 MHz, RFOUT ≈ 4 dBm at 25°C, fREF = 61.44 MHz at 4 dBm, fPFD = 15.36 MHz, Integer PLL Mode LAYOUT Solder the exposed pad on the underside of the ADRF6720-27 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Notice the use of 25 via holes on the exposed pad of the ADRF6720-27 evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Figure 61. Evaluation Board Layout for the ADRF6720-27 Package LO N = 8 N = 1 N = 20 FREQUENCY (MHz) –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 2050 2100 2150 1750 1800 1850 1900 1950 2000 TA = –40°C TA = +25°C TA = +85°C |
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