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ADRF6720-27ACPZ-R7 数据表(PDF) 7 Page - Analog Devices |
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ADRF6720-27ACPZ-R7 数据表(HTML) 7 Page - Analog Devices |
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7 / 44 page  ADRF6720-27 Data Sheet Rev. B | Page 6 of 43 Parameter Test Conditions/Comments Min Typ Max Unit Reference Spurs fPFD −93.2 dBc fPFD × 2 −86.8 dBc fPFD × 3 −89.8 dBc fPFD × 4 −101.7 dBc PHASE NOISE, FREQUENCY = 2140 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −92.9 dBc/Hz 100 kHz offset −116.2 dBc/Hz 1 MHz offset −140.3 dBc/Hz 5 MHz offset −150.7 dBc/Hz 10 MHz offset −151.8 dBc/Hz 20 MHz offset −152.5 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.29 °rms Reference Spurs fPFD −91.3 dBc fPFD × 2 −90.3 dBc fPFD × 3 −85.6 dBc fPFD × 4 −91.0 dBc PHASE NOISE, FREQUENCY = 2300 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −94.6 dBc/Hz 100 kHz offset −114.8 dBc/Hz 1 MHz offset −139.0 dBc/Hz 5 MHz offset −149.4 dBc/Hz 10 MHz offset −151.1 dBc/Hz 20 MHz offset −151.5 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.26 °rms Reference Spurs fPFD −96.1 dBc fPFD × 2 −91.9 dBc fPFD × 3 −88.2 dBc fPFD × 4 −94.8 dBc PHASE NOISE, FREQUENCY = 2600 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −92.4 dBc/Hz 100 kHz offset −111.4 dBc/Hz 1 MHz offset −137.2 dBc/Hz 5 MHz offset −147.7 dBc/Hz 10 MHz offset −148.9 dBc/Hz 20 MHz offset −149.9 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.36 °rms Reference Spurs fPFD −95.5 dBc fPFD × 2 −85.4 dBc fPFD × 3 −93.4 dBc fPFD × 4 −91.0 dBc LO INPUT/OUTPUT LO Output Frequency Range 1 × LO mode 356.25 2855 MHz 2 × LO mode 712.5 5710 MHz LO Output Level 2 × LO or 1 × LO mode, into a 50 Ω load, LO buffer enabled at 2140 MHz LO_DRV_LVL = 0 −5.8 dBm LO_DRV_LVL = 1 −1.0 dBm LO_DRV_LVL = 2 2.2 dBm LO Input Level Externally applied LO, PLL disabled −6 0 +6 dBm LO Input Impedance Externally applied LO, PLL disabled 50 Ω |
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