ADRF6720-27ACPZ-R7 datasheet(20/44 Pages) AD

20 / 44 page

Data Sheet

ADRF6720-27

Rev. B | Page 19 of 43

Table 6. LO Mode Selection

Selection

fVCO or fEXT (MHz)

Quadrature

Generation

QUAD_DIV_EN

(Register 0x01[9])

LO_1XVCO_EN

(Register 0x1[11])

Enables

(Register 0x01[6:0])

VCO_SEL

(Register 0x22[2:0])

Internal

(VCO)

2850 to 3500

Divide by 2

111 111X1

011

3500 to 4020

Divide by 2

111 111X1

010

4020 to 4600

Divide by 2

111 111X1

001

4600 to 5710

Divide by 2

111 111X1

000

2855 to 3000

Polyphase

111 111X1

011

External

700 to 6000

Divide by 2

101 000X1

1XX1

700 to 3000

Polyphase

000 000X1

XXX1

X = don’t care.

LO Frequency and Dividers

The signal coming from the VCO or the external LO inputs

goes through a series of dividers before it is buffered to drive

the active mixers. Two programmable divide by 2 stages divide

the frequency of the incoming signal by 1, 2, or 4 before

reaching the quadrature divider that further divides the signal

frequency by 2 to generate the in-phase and quadrature phase

LO signals for the mixers. The control bits (Register 0x22[4:3])

needed to select the different LO frequency ranges are listed in

Table 7.

Table 7. LO Frequency and Dividers

LO Frequency

Range (MHz)

fVCO/fLO or

fEXTLO/fLO

DIV8_EN

(Register

0x22[4])

DIV4_EN

(Register

0x22[3])

1425 to 2855

712.5 to 1425

356.25 to 712.5

PLL Frequency Programming

The N divider with divide by 2 divides down the VCO signal to

the PFD frequency. The N divider can be configured for

fractional or integer mode by addressing the DIV_MODE bit

(Register 0x02[11]). The default configuration is set for

fractional mode. Use the following equations to determine the

N value and PLL frequency:

VCO

PFD

MOD

FRAC

INT

LO_DIVIDER

DIVIDER

fvco

PFD

where:

fPFD is the phase frequency detector frequency.

fVCO is the VCO frequency.

N is the fractional divide ratio (INT + FRAC/MOD).

INT is the integer divide ratio programmed in Register 0x02.

FRAC is the fractional divider programmed in Register 0x03.

MOD is the modulus divide ratio programmed in Register 0x04.

fLO is the LO frequency going to the mixer core when the loop is

locked.

LO_DIVIDER is the final frequency divider ratio that divides

the frequency of the VCO or the external LO signal down by 2,

4, or 8 before it reaches the mixer, as shown in Table 7.

Loop Filter

The loop filter is connected between the CP and VTUNE pins.

The recommended components for 20 kHz filter designs are

shown in Table 8 and referenced in Figure 44.

The ADRF6720-27 closed-loop phase noise is characterized

using a 20 kHz loop filter. Operation with an external VCO is

possible. In this case, the output of the loop filter is connected

to the tuning pin of the external VCO. The output of the VCO is

brought back into the device on the LOIN+ and LOIN− pins.

For assistance in designing loop filters with other characteristics,

download the most recent revision of ADIsimPLL™ from

www.analog.com/adisimpll.

Table 8. Recommended Loop Filter Components

Component

20 kHz Loop Filter

C57

2700 pF

R12

300 Ω

C58

100 nF

R23

5.6 Ω

C59

2700 pF

R26

820 Ω

C60

1500 pF

PLL Lock Time

It takes time to lock the PLL after the last register is written.

VCO band calibration time and loop settling time are used to

determine the PLL lock time.

After writing to the last register, the PLL automatically performs

a VCO band calibration to choose the correct VCO band. This

calibration takes approximately 94,208 PFD cycles. For a

40 MHz fPFD, this corresponds to 2.36 ms. After a band calibration

completes, the feedback action of the PLL results in the VCO

locking to the correct frequency. The speed to be locked depends

on the nonlinear cycle slipping behavior, as well as the small

signal settling of the loop. For an accurate estimation of the lock

time, download the ADIsimPLL tool to capture these effects

correctly. In general, higher bandwidth loops tend to lock more

quickly than lower bandwidth loops.

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