ADRF6720-27ACPZ-R7 datasheet(21/44 Pages) AD

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ADRF6720-27

Data Sheet

Rev. B | Page 20 of 43

The lock detect signal is available as one of the selectable

outputs through the MUXOUT pin, with a logic high signifying

that the loop is locked. The control bits for the MUXOUT pin

are the REF_MUX_SEL bits (Register 0x21[6:4]), and the

default configuration is for PLL lock detect.

Required PLL/VCO Settings and Register Write Sequence

In addition to writing to the necessary registers to configure the

PLL and VCO for the desired LO frequency and phase noise

performance, the registers listed in Table 9 are the required

registers to write.

To ensure that the PLL locks to the desired frequency, follow the

proper write sequence of the PLL registers. Configure the PLL

registers accordingly to achieve the desired frequency, and the

last writes must be to Register 0x02 (INT_DIV), Register 0x03

(FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02,

VCO calibration initiates, which is the last step to locking the PLL.

Table 9. Required PLL/VCO Register Writes

Address

Bit Name

Setting

Description

0x21[3]

PFD_POLARITY

0x01

Negative polarity

0x49[13:0]

SET_1[13:9],

SET_0[8:0]

0x14B4

Internal settings

External LO Mode

Use the VCO_SEL bits (Register 0x22[2:0]) to select external or

internal LO mode. To configure for external LO mode, set

signals to Pin 33 (LOIN−) and Pin 34 (LOIN+). The external

LO frequency range is 700 MHz to 3 GHz. When the polyphase

phase splitter is selected, a 1 × LO signal is required for the

active mixer, or a 2 × LO can be used with the internal

quadrature divider, as shown in Table 6.

There is also the option of using an external VCO with the

internal PLL. In this case, the PLL is enabled, but the VCO

blocks are turned off.

The LOIN+ and LOIN− input pins must be ac-coupled. When

not in use, leave the LOIN+ and LOIN− pins unconnected.

LO Polarity

The ADRF6720-27 offers the flexibility of specifying the

quadrature polarity on LO to the I channel or Q channel

mixers. This specification determines whether the LO is

injected above or below the RF frequency. RF frequency can

place either above or below the LO depending on the

between the baseband I and Q. For normal operation and

characterization, the Register 0x32 settings are 2 decimal for POL_I

(Register 0x32[9:8]) and 1 decimal for POL_Q (Register 0x32,

Bits[11:10]). Setting Register 0x32 as such places the RF

frequency below the LO (fRF < fLO) when Q leads I and places the

RF frequency above the LO (fRF > fLO) when I leads Q.

Table 10. LO Polarity Setting

Address

Bit

Name

Settings

Description

0x32[11:10]

POL_Q

Quadrature polarity

switch, Q channel

Inverted Q channel

polarity

Normal polarity

0x32[9:8]

POL_I

Quadrature polarity

switch, I channel.

Normal polarity

Inverted I channel

polarity

LO Outputs

The ADRF6720-27 can provide either a differential 1 × or 2 ×

LO output signal at the LOOUT+ and LOOUT− pins (Pin 18

and Pin 19, respectively). The availability of the LO signal

makes it possible to daisy-chain many devices. One ADRF6720-27

device can serve as the master where the LO signal is sourced,

and the subsequent slave devices can share the same LO output

signal from the master.

When the quadrature LO signals are generated using the

quadrature divider, the output signal is available at either 2× or

1× the frequency of the LO signal at the mixer by setting

LO_DRV2X_EN bit (Register 0x1[8]) and DRVDIV2_EN bit

(Register 0x22[5]). However, 1× the frequency of the LO signal

in this case has a phase ambiguity of 180° relative to the LO

signal that drives the mixer core. Because of this phase ambiguity,

the utility of this 1 × LO output signal as a system daisy-chained

LO signal is compromised. To avoid this ambiguity, a second 1×

the frequency of the LO signal output is made available after the

quadrature divider. This second 1 × LO output path is enabled

by setting the LO_DRV1X_EN bit (Register 0x01[7]) high.

When the quadrature LO signals are generated using the

polyphase phase splitter, the output signal is also available at 1×

the frequency of the LO signal by setting LO_DRV1X_EN bit

(Register 0x10[7]) high.

Set the output to different drive levels by accessing the

LO_DRV_LVL bits (Register 0x22[7:6]), as shown in Table 11.

Table 11. LO Output Level at 2140 MHz

LO_DRV_LVL (Register 0x22[7:6])

Amplitude (dBm)

−5.8

−1.0

2.2

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