ADRF6720-27ACPZ-R7 datasheet(19/44 Pages) AD

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ADRF6720-27

Data Sheet

Rev. B | Page 18 of 43

THEORY OF OPERATION

The ADRF6720-27 integrates a high performance broadband

I/Q modulator with a fractional-N PLL and low noise multicore

VCOs. The baseband inputs mix with the LO generated

internally or provided externally, and convert it to a single-

ended RF using an integrated RF balun. A block diagram of the

device is shown in Figure 1. The ADRF6720-27 is programmed

via an SPI.

LO GENERATION BLOCK

The ADRF6720-27 supports the use of both internal and

external LO signals for the mixers. The internal LO is generated

by an on-chip VCO, which is tunable over an octave frequency

range of 2850 MHz to 5710 MHz. The output of the VCO is

phase-locked to an external reference clock through a fractional-N

PLL that is programmable through the SPI control registers. To

produce in-phase and quadrature phase LO signals over the

356.25 MHz to 2855 MHz frequency range to drive the mixers,

steer the VCO outputs through a combination of frequency

dividers, as shown in Figure 42.

Alternatively, an external signal can be used with the dividers or

a polyphase phase splitter to generate the LO signals in quadrature

to the mixers. In demanding applications that require the lowest

possible phase noise performance, it may be necessary to source

the LO signal externally. The different methods of quadrature

LO generation and the control register programming needed

are listed in Table 6.

Internal LO Mode

For internal LO mode, the ADRF6720-27 uses the on-chip PLL

and VCO to synthesize the frequency of the LO signal. The

PLL, shown in Figure 42, consists of a reference path, phase and

frequency detector (PFD), charge pump, and a programmable

integer divider with prescaler. The reference path takes in a

reference clock and divides it down by a factor of 2, 4, or 8, or

multiplies it by a factor of 1 or 2, and then passes it to the PFD.

The PFD compares this signal to the divided down signal from

the VCO. Depending on the PFD polarity selected, the PFD

sends either an up or down signal to the charge pump if the

VCO signal is either slow or fast compared to the reference

frequency. The charge pump sends a current pulse to the off-

chip loop filter to increase or decrease the tuning voltage

(VTUNE).

The ADRF6720-27 integrates four VCO cores, covering an octave

range of 2850 MHz to 5710 MHz.

Table 6 lists the frequency range covered by each VCO. The

desired VCO can be selected by addressing the VCO_SEL bits at

The LO source and quadrature generation path can be selected

by setting the QUAD_DIV_EN bit (Register 0x01[9]) and the

LO_1XVCO_EN bit (Register 0x01[11]).

The mode of the VCO signal through a polyphase filter is

intended to extend the operating frequency with an internal

VCO and is only useful for baseband input frequencies high

enough to prevent the RF output from pulling the VCO.

Figure 42. LO Block Diagram

PFD

CHARGE

PUMP

QUAD

DIVIDER

÷2

N = INT +

FRAC

MOD

POLYPHASE

FILTER

÷1, ÷2,

÷4

LOIN–

VTUNE

EXTERNAL

LOOP

FILTER

LPF

LOIN+

VCO_SEL

REG 0x22[2:0]

DIV8 _EN/

DIV4_EN

REG 0x22[4:3]

DIV_MODE: REG 0x02[11]

INT_DIV: REG 0x02[10:0]

FRAC_DIV: REG 0x03[15:0]

MOD_DIV: REG 0x04[15:0]

CP_CTL

REG 0x20[14:0]

×1

×2

÷8

÷4

÷2

REFIN

MUXOUT

REF_SEL

REG 0x21[2:0]

PFD_POLARITY

REG 0x21[3]

MIXER

QUAD_DIV_EN

REG 0x01[9]

÷2

÷1,

LO_DRV2X_EN

DRVDIV2_EN

REG 0x22[5]

REG 0x01[8]

LO_I+

LO_DRV1X_EN

REG 0x01[7]

LOOUT+

LOOUT–

LOCK_DET

VPTAT

REF_MUX_SEL

REG 0x21[6:4]

LO_1XVCO_EN

REG 0x01[11]

LO_I–

LO_Q+

LO_Q–

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