ADRF6720-27ACPZ-R7 datasheet(24/44 Pages) AD

24 / 44 page

Data Sheet

ADRF6720-27

Rev. B | Page 23 of 43

BASIC CONNECTIONS FOR OPERATION

Figure 44. Basic Connections for Operation (Loop Filter Set to 20 kHz)

Figure 44 shows the basic connections for operating the

ADRF6720-27 as they are implemented on the evaluation board

of the device.

POWER SUPPLY AND GROUNDING

Connect the power supply pins to a 3.3 V source; the pins can

range between 3.15 V and 3.45 V. Individually decouple the pins

using 100 pF and 0.1 µF capacitors located as close as possible

to the pins. Individually decouple the three internal decoupling

nodes (labeled DECL3, DECL2, and DECL1) with capacitors as

shown in Figure 44.

Tie the 11 GND pins to the same ground plane through low

impedance paths.

Solder the exposed pad on the underside of the package to a

ground plane with low thermal and electrical impedance. If the

ground plane spans multiple layers on the circuit board, stitch

them together under the exposed pad. The AN-772 Application

Note discusses the thermal and electrical grounding of the

LFCSP package in detail.

NOTES

1. NIC = NO INTERNAL CONNECTION.

VPOS1

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

0.1µF

(0402)

+3.3V

RED

10µF

(0805)

100pF

(0402)

0.1µF

(0402)

100pF

(0402)

VPOS7

VPOS6

VPOS5

VPOS4

VPOS2

VPOS3

VPOS8

I–

I+

100Ω

(0402)

Q–

Q+

100Ω

(0402)

REFIN

100pF

(0402)

49.9

Ω

(0402)

REF_IN

MUXOUT

(0402)

Ω

100pF

(0402)

100pF

(0402)

EXT LO

VTUNE

C57

2700pF

(0402)

R12

300

Ω

(0402)

C58

100nF

(0603)

C59

2700pF

(0402)

R26

820

Ω

(0402)

C60

1500pF

(0402)

100pF

(0402)

100pF

(0402)

LOOUT

10µF

(0603)

0.1µF

(0402)

100pF

(0402)

SCLK

SDIO

10µF

(0603)

0.1µF

(0402)

100pF

(0402)

10µF

(0603)

0.1µF

(0402)

100pF

(0402)

10k

Ω

(0402)

3.3V

49.9

Ω

(0402)

I+

GND

NIC

ADRF6720-27

REFIN

LDO

VCO

LDO

2.5V

SERIAL PORT

INTERFACE

LO NULLING

DAC

LO NULLING

DAC

PHASE

CORRECTION

PHASE

CORRECTION

×2

×1

÷2

÷4

÷8

LOCK_DET

VPTAT

CHARGE

PUMP

÷2

FRAC

MOD

N = INT +

0°

90°

POLYPHASE

FILTER

÷1, ÷2,

÷4

÷2

ENBL

7 10 16 20 23 25 29 37 38

33 34

RFOUT

LOOUT+

LOOUT–

SCLK

SDIO

DECL3

DECL2

DECL1

I–

Q–

Q+

PFD

R23

5.6

Ω

(0402)

V TO I

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