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STM8AL3136 数据表(PDF) 39 Page - STMicroelectronics |
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STM8AL3136 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 124 page  DocID18474 Rev 7 39/124 STM8AL313x/4x/6x STM8AL3L4x/6x Memory and register map 54 0x00 5055 to 0x00 506F Reserved area (27 bytes) 0x00 5070 DMA1 DMA1_GCSR DMA1 global configuration & status register 0xFC 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 Reserved area (3 bytes) 0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00 0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register (channel 0) 0x00 0x00 5078 DMA1_C0PARH DMA1 peripheral address high register (channel 0) 0x52 0x00 5079 DMA1_C0PARL DMA1 peripheral address low register (channel 0) 0x00 0x00 507A Reserved area (1 byte) 0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register (channel 0) 0x00 0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register (channel 0) 0x00 0x00 507D to 0x00 507E Reserved area (2 bytes) Table 9. General hardware register map (continued) Address Block Register label Register name Reset status |
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