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STM8AL3136 数据表(PDF) 42 Page - STMicroelectronics |
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STM8AL3136 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 124 page  Memory and register map STM8AL313x/4x/6x STM8AL3L4x/6x 42/124 DocID18474 Rev 7 0x00 50A9 to 0x00 50AF Reserved area (7 bytes) 0x00 50B0 RST RST_CR Reset control register 0x00 0x00 50B1 RST_SR Reset status register 0x01 0x00 50B2 PWR PWR_CSR1 Power control and status register 1 0x00 0x00 50B3 PWR_CSR2 Power control and status register 2 0x00 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK CLK_DIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 0x00 50C7 CLK_SCSR System clock status register 0x01 0x00 50C8 CLK_SWR System clock switch register 0x01 0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000 0x00 50CA CLK_CSSR Clock security system register 0x00 0x00 50CB CLK_CBEEPR Clock BEEP register 0x00 0x00 50CC CLK_HSICALR HSI calibration register 0xxx 0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x 0x00 50D0 to 0x00 50D2 Reserved area (3 bytes) 0x00 50D3 WWDG WWDG_CR WWDG control register 0x7F 0x00 50D4 WWDG_WR WWDR window register 0x7F 0x00 50D5 to 00 50DF Reserved area (11 bytes) 0x00 50E0 IWDG IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF Table 9. General hardware register map (continued) Address Block Register label Register name Reset status |
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