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STM8AF6213 数据表(PDF) 72 Page - STMicroelectronics |
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STM8AF6213 数据表(HTML) 72 Page - STMicroelectronics |
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72 / 106 page ![]() Electrical characteristics STM8AF6213/23/23A/26 72/106 DocID025118 Rev 5 9.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 47. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage - -0.3 V - 0.3 x VDD V VIH Input high level voltage 0.7 x VDD -VDD + 0.3 V Vhys Hysteresis(1) -700 - mV Rpu Pull-up resistor VDD = 5 V, VIN = VSS 35 55 80 k tR, tF Rise and fall time (10% - 90%) Fast I/Os Load = 50 pF -- 35(2) ns Standard and high sink I/Os Load = 50 pF -- 125(2) Fast I/Os Load = 20 pF 20(2) Standard and high sink I/Os Load = 20 pF 50(2) Ilkg Digital input pad leakage current VSS VIN VDD -- ±1(3) µA Ilkg ana Analog input pad leakage current VSS VIN VDD -40 °C < TA < 125 °C -- ±250(3) nA VSS VIN VDD -40 °C < TA < 150 °C -- ±500(3) Ilkg(inj) Leakage current in adjacent I/O(2) Injection current ±4 mA - - ±1(3) µA 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data based on characterization results, not tested in production. 3. Guaranteed by design. |
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