STM8AF6213 datasheet(48/106 Pages) STMICROELECTRONICS

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Option bytes

STM8AF6213/23/23A/26

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DocID025118 Rev 5

8.1

Option byte description

Table 15. Option byte description

Option byte no.

Description

OPT0

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)



Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers

reference manual (RM0016) section on Flash/EEPROM memory

readout protection for details.

OPT1

UBC[7:0]: User boot code area

0x00: No UBC, no write-protection



0x01: Page 0 defined as UBC, memory write-protected



0x02: Page 0 to 1 defined as UBC, memory write-protected



Pages 0 and 1 contain the interrupt vectors.



...

0x7F: Pages 0 to 126 defined as UBC, memory write-protected



Other values: Page 0 to 127 defined as UBC, memory write-protected.

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers

reference manual (RM0016) section on Flash/EEPROM write protection

for more details.

OPT2

AFR[7:0]

Refer to the following sections for the alternate function remapping

descriptions of bits [7:2] and [1:0] respectively.

OPT3

HSITRIM: high-speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN: low-speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG independent watchdog activated by software

1: IWDG independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on Halt

0: No reset generated on Halt if WWDG active

1: Reset generated on Halt if WWDG active

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