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STM32L475VC 数据表(PDF) 166 Page - STMicroelectronics |
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STM32L475VC 数据表(HTML) 166 Page - STMicroelectronics |
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166 / 193 page ![]() Electrical characteristics STM32L475xx 166/193 DocID027692 Rev 2 Figure 28. Quad SPI timing diagram - SDR mode Figure 29. Quad SPI timing diagram - DDR mode Table 85. QUADSPI characteristics in DDR mode(1) Symbol Parameter Conditions Min Typ Max Unit FCK 1/t(CK) Quad SPI clock frequency 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 -- 40 MHz 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 -- 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 -- 48 1.71 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 -- 26 tw(CKH) Quad SPI clock high and low time fAHBCLK = 48 MHz, presc=0 t(CK)/2-2 - t(CK)/2 ns tw(CKL) t(CK)/2 - t(CK)/2+2 tsf(IN);tsr(IN) Data input setup time Voltage Range 1 and 2 3.5 - - thf(IN); thr(IN) Data input hold time 6.5 - - tvf(OUT);tvr(OUT) Data output valid time Voltage Range 1 - 11 12 Voltage Range 2 15 19 thf(OUT); thr(OUT) Data output hold time Voltage Range 1 6 - - Voltage Range 2 8 - 1. Guaranteed by characterization results. |
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