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STM32L475VC 数据表(PDF) 168 Page - STMicroelectronics |
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STM32L475VC 数据表(HTML) 168 Page - STMicroelectronics |
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168 / 193 page  Electrical characteristics STM32L475xx 168/193 DocID027692 Rev 2 Figure 30. SAI master timing waveforms tv(SD_B_ST) Data output valid time Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 -22 ns Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 -34 th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns tv(SD_A_MT) Data output valid time Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 -27 ns Master transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 -40 th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. Table 86. SAI characteristics(1) (continued) Symbol Parameter Conditions Min Max Unit |
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