USB84604 datasheet(25/61 Pages) MICROCHIP

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 2014-2016 Microchip Technology Inc.

DS60001295C-page 25

USB84604

5.1

Boot Sequence

5.1.1

STANDBY MODE

If the external hardware reset is asserted, the hub will be in Standby Mode. This mode provides a very low power state

for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all internal

regulators are powered off, the PLL is not running, and core logic is powered down in order to minimize power consump-

tion. Because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized

after RESET_N is negated high.

5.1.2

HARDWARE INITIALIZATION STAGE (HW_INIT)

The first stage is the initialization stage and occurs on the negation of RESET_N. In this stage the 1.2 V regulator is

enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK is supplied. Configuration registers

are initialized to their default state and strap input values are latched. The device will complete initialization and auto-

matically enter the next stage. Because the digital logic within the device is not yet stable, no communication with the

device using the SMBus is possible. Configuration registers are initialized to their default state.

If there is a REFCLK present, the next state is SW_INIT.

5.1.3

SOFTWARE INITIALIZATION STAGE (SW_INIT)

Once the hardware is initialized, the firmware can begin to execute. The internal firmware checks for an external SPI

ROM. The firmware looks for an external SPI flash device that contains a valid signature of “2DFU” (device firmware

upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code

execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues

from internal ROM. SPI ROMs used with the device must be 1 Mbit and support either 30 MHz or 60 MHz. The frequency

used is set using the SPI_SPD_SEL configuration strap. Both 1- and 2-bit SPI operation is supported. For optimum

throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are also supported. Refer to Sec-

tion 6.3.2, "SPI Speed Select (SPI_SPD_SEL)," on page 30 for additional information on selection of the SPI speed.

For all other configurations, the firmware checks for the presence of an external I2C/SMBus. It does this by asserting

two pull down resistors on the data and clock lines of the bus. The pull downs are 50 kΩ. If there are 10 kΩ pull-ups

present, the device becomes aware of the presence of an external SMBus/I2C bus. If a bus is detected, the firmware

transitions to the SOC_CFG state.

5.1.4

SOC CONFIGURATION STAGE (SOC_CFG)

In this stage, the SOC may modify any of the default configuration settings specified in the integrated ROM such as USB

device descriptors, or port electrical settings.

There is no time limit. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When the SOC

has completed configuring the device, the Attach command (AA55h) must be sent. Refer to the application note SMBus

Slave Interface for the USB253x/USB3x13/USB46x4 [ 7].

5.1.5

HUB CONFIGURATION STAGE (HUB_CFG)

Once the SOC has indicated that it is done with configuration, then all the configuration data is combined. The default

data, the SOC configuration data, the OTP data are all combined in the firmware and the device is programmed. If the

SOC_CFG state is evaluated, and the OTP data will be added to the SOC settings.

After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present. If

VBUS is present, and upstream battery charging is not enabled, the device will transition to the Connect (Hub.Connect)

stage.

5.1.6

HUB CONNECT STAGE (HUB.CONNECT)

Once the CHGDET stage is completed, the device enters the Hub.Connect stage. The Hub connect stage is when the

Hub will begin operation according to the USB 2.0 Specification [ 2]. The Hub will monitor the VBUS_DET pin, and when

the signal is high, it will enable the 1.5 kΩ PU on DP and enumerate with the Host.

Note:

OTP can overwrite any configuration the SOC did as shown in Figure 5-1.

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