USB84604 datasheet(32/61 Pages) MICROCHIP

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USB84604

DS60001295C-page 32

 2014-2016 Microchip Technology Inc.

After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI

controller will clock out one more byte. If the address is anything other than one more than the last address, the SPI

controller will terminate the transaction by driving SPI_CE_N high. As long as the addresses are sequential, the SPI

controller will continue clocking data in.

7.1.3

32 BYTE CACHE

There is a 32-byte pipeline cache with an associated base address pointer and length pointer. Once the SPI controller

detects a jump, the base address pointer is initialized to that address. As each new sequential data byte is fetched, the

data is written into the cache and the length is incremented. If the sequential run exceeds 32 bytes, the base address

pointer is incremented to indicate the last 32 bytes fetched. If the firmware performs a jump, and the jump is in the cache

address range, the fetch is done in 1 clock from the internal cache instead of an external access.

7.1.4

INTERFACE OPERATION TO THE SPI PORT WHEN NOT PERFORMING FAST READS

There is a 8-byte command buffer (SPI_CMD_BUF[7:0]), an 8-byte response buffer (SPI_RESP_BUF[7:0]), and a

length register that counts out the number of bytes (SPI_CMD_LEN). Additionally, there is a self-clearing GO bit in the

SPI_CTL register. Once the GO bit is set, device drives SPI_CE_N low and starts clocking. It will then output SPI_CM-

D_LEN x 8 number of clocks. After the first COMMAND byte has been sent out, the SPI_DI input is stored in the

SPI_RESP buffer. If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO out-

put.

This mode is used for program execution out of internal RAM or ROM.

Automatic reads and writes happen when there is an external XDATA read or write, using the serial stream that has

been previously discussed.

FIGURE 7-2:

SPI DUAL HI-SPEED READ SEQUENCE

SPI_CE_N

SPI_CLK

SPI_DO

SPI_DI

MSB

HIGH IMPEDANCE

15 16

12 3 4

ADD.

23 24

ADD.

39 40

31 32

47 48

51 52

55 56

NN+1

N+2

N+3

N+4

MSB

N+1

N+2

N+3

N+4

MSB

Bits-7,5,3,1

Bits-6,4,2,0

Bits-6,4,2,0 Bits-6,4,2,0

Bits-6,4,2,0

Bits-7,5,3,1

Bits-6,4,2,0

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