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AD8067ART-R2 数据表(PDF) 16 Page - Analog Devices

部件名 AD8067ART-R2
功能描述  High Gain Bandwidth Product Precision Fast FET??Op Amp
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8067ART-R2 数据表(HTML) 16 Page - Analog Devices

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AD8067
Rev. 0 | Page 16 of 24
For inverting voltage gain applications, the source impedance of the
input signal must be considered because that will set the applica-
tion’s noise gain as well as the apparent closed-loop gain. The basic
frequency equation for inverting applications is below.
VI
RS
SIGNAL SOURCE
+
+
VOUT
+
CPAR
CPAR
RG
CD
CM
CM
RF
S
G
F
S
G
R
R
R
R
R
(GBP)
Frequency
dB
Loop
Closed
+
+
+
×
=
3
S
G
F
R
R
R
Gain
DC
+
=
Figure 43. Input and Board Capacitances
GBP is the gain bandwidth product of the amplifier, and RS is the
signal source resistance.
There will be a pole in the feedback loop response formed by the
source impedance seen by the amplifier’s negative input (RG RF)
and the sum of the amplifier’s differential input capacitance,
common-mode input capacitance, and any board parasitic
capacitance. This will decrease the loop phase margin and can
cause stability problems, i.e., unacceptable peaking and ringing
in the response. To avoid this problem it is recommended that the
resistance at the AD8067’s negative input be kept below 200 for
all wideband voltage gain applications.
S
G
S
G
F
R
R
R
R
R
Gain
Noise
ion
Configurat
Inverting
+
+
+
=
It is important that the noise gain for inverting applications be kept
above 6 for stability reasons. If the signal source driving the inverter
is another amplifier, take care that the driving amplifier shows low
output impedance through the frequency span of the expected
closed-loop bandwidth of the AD8067.
Matching the impedances at the inputs of the AD8067 is also
recommended for wideband voltage gain applications. This will
minimize nonlinear common-mode capacitive effects that can
significantly degrade settling time and distortion performance.
Resistor Selection for Wideband
Operation
Voltage feedback amplifiers can use a wide range of resistor values
to set their gain. Proper design of the application’s feedback
network requires consideration of the following issues:
The AD8067 has a low input voltage noise of 6.6 nV/√Hz. Source
resistances greater than 500 at either input terminal will notably
increase the apparent Referred to Input (RTI) voltage noise of the
application.
• Poles formed by the amplifier’s input capacitances with the
resistances seen at the amplifier’s input terminals
• Effects of mismatched source impedances
The amplifier must supply output current to its feedback network,
as well as to the identified load. For instance, the load resistance
presented to the amplifier in Figure 40 is RLOAD  (RF + RG). For an
RLOAD of 100 Ω, RF of 1 k, and RG of 100 Ω, the amplifier will be
driving a total load resistance of about 92 Ω. This becomes more of
an issue as RF decreases. The AD8067 is rated to provide 30 mA of
low distortion output current. Heavy output drive requirements
also increase the part’s power dissipation and should be taken
into account.
• Resistor value impact on the application’s output
voltage noise
• Amplifier loading effects
The AD8067 has common-mode input capacitances (CM) of 1.5 pF
and a differential input capacitance (CD) of 2.5 pF. This is illustrated
in Figure 43. The source impedance driving the positive input of a
noninverting buffer will form a pole primarily with the amplifier’s
common-mode input capacitance as well as any parasitic
capacitance due to the board layout (CPAR). This will limit the
obtainable bandwidth. For G = +10 buffers, this bandwidth limit
will become apparent for source impedances >1 kΩ.



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