AD8067

Rev. 0 | Page 17 of 24

DC ERROR CALCULATIONS

Input and Output Overload Behavior

Figure 44 illustrates the primary dc errors associated with a voltage

feedback amplifier. For both inverting and noninverting

configurations:

A simplified schematic of the AD8067 input stage is shown in

Figure 45. This shows the cascoded N-channel JFET input pair,

the ESD and other protection diodes, and the auxiliary NPN

input stage that eliminates phase inversion behavior.













+

=

G

F

G

OS

OS

R

R

R

V

V

to

due

Error

Voltage

Output

When the common-mode input voltage to the amplifier is driven

to within approximately 3 V of the positive power supply, the input

JFET’s bias current will turn off, and the bias of the NPN pair will

turn on, taking over control of the amplifier. The NPN differential

pair now sets the amplifier’s offset, and the input bias current is

now in the range of several tens of microamps. This behavior is

illustrated in Figure 25 and Figure 26. Normal operation resumes

when the common-mode voltage goes below the 3 V from the

positive supply threshold.

F

–

B

G

G

F

S

B

B

R

I

–

R

R

R

R

I

I

to

due

Error

Voltage

Output

×













+

×

Total error is the sum of the two.

DC common-mode and power supply effects can be added by

CMR

∆V

PSR

∆V

(nom)

V

(tot)

V

CM

S

OS

OS

+

+

=

The output transistors have circuitry included to limit the extent

of their saturation when the output is overdriven. This improves

output recovery time. A plot of the output recovery time for the

AD8067 used as a G = +10 buffer is shown in Figure 17.

is the offset voltage specified at nominal conditions

nominal conditions. PSR is power supply rejection (90 dB

nominal test conditions. CMR is common-mode rejection (85 dB

minimum for the AD8067).

SWITCH

CONTROL

TO REST OF AMP

–

+

+

–

+

Figure 44. Op Amp DC Error Sources

Figure 45. Simplified Input Schematic