AD8067

Rev. 0 | Page 23 of 24

AD8067

C2

0.1

µF

1

C1

10

µF

+5V

–5V

5

2

4

3

AD8009

C8

0.1

µF

6

C7

10

µF

+5V

7

2

3

4

C11

0.1

µF

C9

10

µF

–5V

C4

0.1

µF

C3

10

µF

INPUT

R4

200

Ω

R3

21.5

Ω

OUTPUT

R5

50

Ω

R1

51.1

Ω

R2

4.99k

Ω

C6

0.001

µF

C10

0.001

µF

C5

5pF

M 25ns CH1 0V

T

C1 AMPL

4V

Figure 59. Large Signal Response

M 25ns CH1 0V

C1 AMPL

480mV

T

The composite amplifier is set for a gain of 100. The overall gain is

set by the following equation:

1

1

2 +

=

R

R

V

V

I

O

The output stage is set for a gain of +10; therefore, the AD8067 has

an effective gain of +10, thereby allowing it to a maintain

bandwidth in excess of 55 MHz.

The circuit can be tailored for different gain values; keeping the

ratios roughly the same will ensure that the bandwidth integrity is

maintained. Depending on the board layout, capacitor C5 may be

required to reduce ringing on the output. The gain bandwidth and

pulse responses are shown in Figure 58, Figure 59, and Figure 60.

Figure 60. Small Signal Response

Layout of this circuit requires attention to the routing and length of

the feedback path. It should be kept as short as possible to

minimize stray capacitance.

FREQUENCY – MHz

44

24

26

28

30

32

34

36

38

40

42

0.1

1

10

100

Figure 58. Gain Bandwidth Response