Copyright © 2013 Future Technology Devices International Limited

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FT221X USB 8-BIT SPI/FT1248 IC Datasheet

Version 1.3

Document No.: FT_000630 Clearance No.: FTDI# 263

5 FT1248 Interface Description.

The FT1248 protocol has a dynamic bi-directional data bus interface that can be configured as 1, 2, 4, or

8-bits wide providing users with the flexibility to configure the interface with performance, pin count and

PCB area in mind. For example, 1-bit mode it requires 8 clock cycles to get 8 data bits and in 8-bit mode

all 8 bits are sent with one clock.

In the FT1248 there are 3 distinct phases:

While CS# is inactive, the FT1248 reflects the status of the write buffer and read buffers within the

FT221X on the MIOSIO[0] and MISO wires respectively. The buffers are 512 Bytes each and the status

will reflect if at least one byte of space is available for the external device to write to and whether at least

one byte is available to be read by the external device.

Additionally, the FT1248 slave block supports multiple slave devices where a master can communicate

with multiple SPI slave devices. When the slave is sharing buses with other SPI slave devices, the write

and read buffer status cannot be reflected on the MIOSIO[0] and MISO wires during SS_n inactivity as

this would cause bus contention. Therefore, it is possible for the user to select whether they wish to have

the buffer status switched on or off during inactivity.

FT1248 mode).

When CS# is active a command/bus size phase occurs first. Following the command phase is the data

phase, for each data byte transferred the FT1248 slave drives an ACK/NAK status onto the MISO wire.

The master can send multiple data bytes so long as CS# is active, if an unsuccessful data transfer occurs,

i.e. a NAK happens on the MISO wire then the master should immediately abort the transfer by de-

asserting CS#.

Figure 5.1: FT1248 Basic Waveform Protocol.

5.1 Determining the Dynamic Bus Width

The bus width is dynamic. In order for the FT221X, in FT1248 mode, to determine the bus width within

the command phase, the bus width is encoded along with the actual commands on the first active clock

edge when CS# is active and has a data width of 8-bits.



If any of the MIOSIO[7:4] signals are driven low by the external host then the data transfer width

equals 8-bits



If any of the MIOSIO[3:2] signals are driven low by the external host then the data transfer width

equals 4-bits



If MIOSIO[1] signal is driven low by the external host then the data transfer width equals 2-bits



Else the bus width is defaulted to 1-bit

In order to successfully decode the bus width, all MIOSIO signals must have pull up resistors. By default,

all MIOSIO signals shall be seen by the FT221X in FT1248 mode as logic ‘1’from the internal resistors.

This means that when a FT1248 master does not wish to use certain MIOSIO signals, the slave (FT221X)

is still capable of determining the requested bus width since any unused MIOSIO signals shall be pulled

up by default.

The remaining bits used during the command phase are used to contain the command itself which means

that it is possible to define up to 16 unique commands.