FT221XS-R datasheet(16/45 Pages) FTDI

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FT221X USB 8-BIT SPI/FT1248 IC Datasheet

Version 1.3

Document No.: FT_000630 Clearance No.: FTDI# 263

buffer

address eeprom

0x05

Address EEPROM command sets the address users wish to

write or read from

write eeprom

0x06

Write EEPROM command sets the write data to be written into

the EEPROM

read eeprom

0x07

Read EEPROM command reads

read usb status

0x08

Read USB Status:

00 = suspended, 01 = default, 10 = addressed, 11 =

configured

Reserved

0x09

– 0xF

Unused Commands

Table 5.1: FT1248 Commands

5.3 LSB or MSB Selection

The data can be sent/received Least Significant Bit First (LSB) or Most Significant Bit First (MSB). To

determine which mode is used by the FT1248 interface of the FT221X the MTP memory must be set.

This may be selected with FT_PROG.

5.4 Clock Phase/Polarity

The FT1248 slave does not need to have any knowledge of clock rate as this is supplied by the FT1248

master. However the relationship between clock and data needs to be controllable, to allow the slave to

operate in the same way as the master such that data is correctly driven and sampled on the correct

clock phases. By configuring the polarity and phase of CLK with respect to the data it is possible to match

the FT1248 master.

There are 4 possible modes which are determined by the Clock Polarity (CPOL) and Clock Phase (CPHA)

signals. The different combinations of these signals are commonly referred to as modes, see Table 5.2

below. For the FT1248 slave, only 2 of these 4 modes are supported. CPHA will always be set to 1 in the

FT1248 slave because data is available or driven on to MIOSIO wires on the first clock edge after CS# is

active and is therefore sampled on the trailing edge of the first clock pulse. When CPHA equals 0, it

means data must be available or driven onto the MIOSIO wires on the first leading edge of the clock after

CS# is active. However, during this period between CS# becoming active and the first leading clock edge

is when the MIOSIO wires are being “turned around” as when CS# is inactive the FT1248 slave is driving

the write buffer status. Supporting CPHA = 0 would result in bus contention and therefore, shall not be

supported.

Mode

CPOL

CPHA

Supported

YES

Table 5.2: CPOL & CPHA Mode Numbers

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