Copyright © 2013 Future Technology Devices International Limited

17

FT221X USB 8-BIT SPI/FT1248 IC Datasheet

Version 1.3

Document No.: FT_000630 Clearance No.: FTDI# 263

When CPOL is 1, the idle state of the clock is high. When CPOL is 0, the idle state of the clock is low. It

should be noted that clock phase and polarity need to be identical for the master and attached slave

device.

5.4.1 CPHA = 1

When CPHA is set to ‘1’, the first edge after CS# goes low will be used to shift (or drive) the first data bit

onto MIOSIO. Every odd numbered edge after this will shift out the next data bit. Incoming data will be

sampled on the second or trailing SCLK edge and every even edge thereafter.

Figure 5.3: FT1248 Clock Format CPHA = 1

Note: The CPOL value may be selected in the MTP memory. This may be done with FT_PROG.

Note: Further information on this interface can be found in AN_167_FT1248 Parallel Serial Interface

Basics from the FTDI website www.ftdichip.com.

SCK (CPOL = 0)

SCK (CPOL = 1)

start

end

SS_n

SCK Edge No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CPHA = 1

MISO

MOSI

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Sample

Transfer

end of idle

start of

next idle