FT313HQ-R datasheet(15/67 Pages) FTDI

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Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bus Mode

ALE/ADV_N

CLE

DATA_BUS

_WIDTH

Signal Description

select: control signals

 DACK: DMA acknowledge input

 DREQ: DMA request output

General

Multiplex 16-bit

LOW

HIGH

 AD[15:0]: 16-bit data bus

 ALE, write(WR_N), read(RD_N), chip

select: control signals

 DACK: DMA acknowledge input

 DREQ: DMA request output

Table 4-1 Bus Configuration modes

SRAM mode

NOR mode

General

Multiplex

mode

Type

Description

AD[15:0]

I/O

Data or address bus

A[7:0]

Address bus

ADV_N

ALE

Address or command valid

CS_N

Chip select

RD_N/RE_N

OE_N

RD_N/RE_N

Read control

WR_N/WE_N

WE_N

WR_N/WE_N

Write control

INT

Interrupt request

DREQ

DMA request

DACK

DMA acknowledge

Table 4-2 Pin information of the bus interface

4.2 SRAM bus interface mode

The bus interface will be in SRAM 16-bit mode if pins ALE/ADV_N and CLE are HIGH, when:

•

The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW.

Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in SRAM 8-bit mode.

In SRAM mode, A[7:0] is the 8-bit address bus and AD[15:0] is the separate 16-bit data bus.

The FT313H pins RD_N /RE_N/OE_N and WR_N/WE_N are the read and write strobes. The

SRAM bus interface supports both 8-bit and 16-bit bus width that can be configured by setting

or clearing bit DATA_BUS_WIDTH. The DMA transfer is also applicable to this interface.

FT313HQ-R 数据表(PDF) 15 Page - Future Technology Devices International Ltd.

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