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FT313HQ-R 数据表(PDF) 5 Page - Future Technology Devices International Ltd. |
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FT313HQ-R 数据表(HTML) 5 Page - Future Technology Devices International Ltd. |
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5 / 67 page ![]() Copyright © 2013 Future Technology Devices International Limited 5 Document No.: FT_000589 FT313H USB2.0 HS Host Controller Datasheet Version 1.2 Clearance No.: FTDI# 318 5.2.10 POSTSC register (address = 30h)............................................................................. 27 5.3 Configuration registers ..................................................................... 29 5.3.1 EOTTIME register (address = 34h) ............................................................................... 29 5.3.2 CHIPID register (address = 80h) ................................................................................. 30 5.3.3 HWMODE register (address = 84h) .............................................................................. 30 5.3.4 EDGEINTC register (address = 88h) ............................................................................. 31 5.3.5 SWRESET register (address = 8Ch).............................................................................. 31 5.3.6 MEMADDR register (address = 90h) ............................................................................. 33 5.3.7 DATAPORT register (address = 92h) ............................................................................ 33 5.3.8 DATASESSION register (address = 94h) ....................................................................... 33 5.3.9 CONFIG register (address = 96h) ................................................................................ 33 5.3.10 AUX_MEMADDR register (address = 98h) .................................................................. 35 5.3.11 AUX_DATAPORT register (address = 9Ah) ................................................................. 35 5.3.12 SLEEPTIMER register (address = 9Ch) ...................................................................... 35 5.4 Interrupt registers............................................................................ 35 5.4.1 HCINTSTS register (address = A0h) ............................................................................. 35 5.4.2 HCINTEN register (address = A4h)............................................................................... 37 5.5 USB testing registers ........................................................................ 38 5.5.1 TESTMODE register (address = 50h) ............................................................................ 38 5.5.2 TESTPMSET1 register (address = 70h) ......................................................................... 39 5.5.3 TESTPMSET2 register (address = 74h) ......................................................................... 39 6 Devices Characteristics and Ratings ........................................... 40 6.1 Absolute Maximum Ratings............................................................... 40 6.2 DC Characteristics............................................................................. 41 6.3 AC Characteristics............................................................................. 44 6.4 Timing .............................................................................................. 46 6.4.1 PIO timing ................................................................................................................ 46 6.4.2 DMA timing ............................................................................................................... 52 7 Application Examples ................................................................. 53 7.1 Examples of Bus Interface connection .............................................. 54 7.1.1 16-Bit SRAM asynchronous bus interface ...................................................................... 54 7.1.2 8-Bit SRAM asynchronous bus interface ........................................................................ 54 7.1.3 16-Bit NOR asynchronous bus interface ........................................................................ 55 7.1.4 8-Bit NOR asynchronous bus interface.......................................................................... 55 7.1.5 16-Bit General Multiplex asynchronous bus interface ...................................................... 55 7.1.6 8-Bit General Multiplex asynchronous bus interface........................................................ 56 8 Package Parameters................................................................... 57 8.1 FT313H Package Markings ................................................................ 57 8.1.1 QFN-64 .................................................................................................................... 57 8.1.2 LQFP-64 ................................................................................................................... 58 |
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