TNETV2685FIBZUT7 datasheet(164/191 Pages) TI1

164 / 191 page

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the

GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when

an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by

inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

In networking systems, packet transmission and reception are critical tasks. The communications port

programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software

and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory

that holds up to 512 buffer descriptors.

After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet

transmit and receive operations.

•

Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head

descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first

packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to

process before sending to the SGMII.

•

Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head

descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the

CPPI protocol.

DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses

0x02D0 0000 - 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The

Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code (0x4C6F436B)

and a 32-bit unlock code (0x6F50654E) written to ESS_LOCK register will activate or clear this option,

respectively. See Section 3.2.5 and Section 3.2.7

The 3-port gigabit switch block contains the following functions:

•

3-port gigabit switch: performs packet forwarding and routing functions, one port is internally connected

to the C64x+ DSP and two ports are brought out externally

•

CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including

channel setup and channel teardown

•

GMAC (Gigabit Ethernet MAC):

–

Uses Rx packet FIFO, and a TX packet FIFO to improve data transfer efficiency

–

Handles processing of Ethernet packet data, frames, and headers

–

Includes flow control

–

Provides statistics collection and reporting

•

The address lookup engine (ALE) processes all received packets to determine where (that is, which

packet location) to forward the packet. The ALE uses the incoming packet received port number,

destination address, source address, length/type, and VLAN information to determine how the packet

should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which port(s)

the packet should be forwarded.

6.19.2 Interrupt Controller and Pacing Interrupts

The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for

output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected

from the miscellaneous interrupts (host error level, statistics level, MDIO User [2], MDIO link [2]).

The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the

miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that

occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very

high rate, the performance benefit is significant due to minimizing the overhead associated with servicing

each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of

times that large interrupt service routines are moved to and from the DSP instruction cache.

MDIO

164

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): TMS320DM647 TMS320DM648

TNETV2685FIBZUT7 数据表(PDF) 164 Page - Texas Instruments

TNETV2685FIBZUT7 数据表(HTML) 164 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载