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TNETV2685FIBZUT7 数据表(PDF) 165 Page - Texas Instruments |
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TNETV2685FIBZUT7 数据表(HTML) 165 Page - Texas Instruments |
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165 / 191 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 The MDIO module manages the PHY configuration and monitors status. For a list of supported registers and register fields, see Table 6-79. In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower nibble. SGMII The SGMII/SerDes module contains: • Gigabit differential current mode logic (CML) receiver/transmitters • An integrated RX/TX PLL to provide the required high-quality/high-speed internal clocks • Phase-interpolator-based clock/data recovery • A bandgap reference for transmitter swing settings • Parallel-to-serial converter • Serial-to-parallel converter • Integrated receiver and transmitter termination • Configuration logic • 802.3 auto-negotiation functionality (as defined in Clause 37 of the IEEE Specification 802.3) The SGMII receive interface converts the encoded receive signals from the differential receive input terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals. The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as an error by an error CRC. NOTE SGMII1 is pinned out only in the DM648 device. The DM647 device has only one SGMII port (SGMII0). 6.19.3 Peripheral Register Description(s) Table 6-78 through Table 6-81 list the registers. Table 6-78. Ethernet Switch Registers HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x02D0 3000 CPSW_ID_VER CPSW Identification and Version Register 0x02D0 3004 CPSW_CONTROL CPSW Switch Control Register 0x02D0 3008 CPSW_SOFT_RESET CPSW Soft Reset Register 0x02D0 300C CPSW_STAT_PORT_EN CPSW Statistics Port Enable Register 0x02D0 3010 CPSW_PTYPE CPSW Transmit Priority Type Register 0x02D0 3014 P0_MAX_BLKS CPSW Port 0 Maximum FIFO blocks Register 0x02D0 3018 P0_BLK_CNT CPSW Port 0 FIFO Block Usage Count Register (read only) 0x02D0 301C P0_FLOW_THRESH CPSW Port 0 Flow Control Threshold Register 0x02D0 3020 P0_PORT_VLAN CPSW Port 0 VLAN Register 0x02D0 3024 P0_TX_PRI_MAP CPSW Port 0 Tx Header Pri to Switch Pri Mapping Register 0x02D0 3028 GMAC0_GAP_THRESH CPSW GMAC0 Short Gap Threshold Register 0x02D0 302C GMAC0_SA_LO CPSW GMAC0 Source Address Low Register 0x02D0 3030 GMAC0_SA_HI CPSW GMAC0 Source Address High Register 0x02D0 3034 P1_MAX_BLKS CPSW Port 1 Maximum FIFO blocks Register 0x02D0 3038 P1_BLK_CNT CPSW Port 1 FIFO Block Usage Count Register (read only) 0x02D0 303C P1_FLOW_THRESH CPSW Port 1 Flow Control Threshold Register 0x02D0 3040 P1_PORT_VLAN CPSW Port 1 VLAN Register Copyright © 2007–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 165 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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