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TNETV2685FIBZUT7 数据表(PDF) 168 Page - Texas Instruments |
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TNETV2685FIBZUT7 数据表(HTML) 168 Page - Texas Instruments |
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168 / 191 page  TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com Table 6-78. Ethernet Switch Registers (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x02D0 3234 RX5_HDP CPDMA Rx 5 Channel 5 Head Desc Pointer 0x02D0 3238 RX6_HDP CPDMA Rx 6 Channel 6 Head Desc Pointer 0x02D0 323C RX7_HDP CPDMA Rx 7 Channel 7 Head Desc Pointer 0x02D0 3240 TX0_CP CPDMA Tx Channel 0 Completion Pointer Register 0x02D0 3244 TX1_CP CPDMA Tx Channel 1 Completion Pointer Register 0x02D0 3248 TX2_CP CPDMA Tx Channel 2 Completion Pointer Register 0x02D0 324C TX3_CP CPDMA Tx Channel 3 Completion Pointer Register 0x02D0 3250 TX4_CP CPDMA Tx Channel 4 Completion Pointer Register 0x02D0 3254 TX5_CP CPDMA Tx Channel 5 Completion Pointer Register 0x02D0 3258 TX6_CP CPDMA Tx Channel 6 Completion Pointer Register 0x02D0 325C TX7_CP CPDMA Tx Channel 7 Completion Pointer Register 0x02D0 3260 RX0_CP CPDMA Rx Channel 0 Completion Pointer Register 0x02D0 3264 RX1_CP CPDMA Rx Channel 1 Completion Pointer Register 0x02D0 3268 RX2_CP CPDMA Rx Channel 2 Completion Pointer Register 0x02D0 326C RX3_CP CPDMA Rx Channel 3 Completion Pointer Register 0x02D0 3270 RX4_CP CPDMA Rx Channel 4 Completion Pointer Register 0x02D0 3274 RX5_CP CPDMA Rx Channel 5 Completion Pointer Register 0x02D0 3278 RX6_CP CPDMA Rx Channel 6 Completion Pointer Register 0x02D0 327C RX7_CP CPDMA Rx Channel 7 Completion Pointer Register 0x02D0 3280 - 0x02D0 32BF reserved 0x02D0 32C0 - 0x02D0 32FC reserved 0x02D0 3300 - 0x02D0 337C reserved 0x02D0 3380 - 0x02D0 33FC reserved 0x02D0 3400 RXGOODFRAMES CPSW_STATS Total number of good frames received 0x02D0 3404 RXBROADCASTFRAMES CPSW_STATS Total number of good broadcast frames received 0x02D0 3408 RXMULTICASTFRAMES CPSW_STATS Total number of good multicast frames received 0x02D0 340C RXPAUSEFRAMES CPSW_STATS PauseRxFrames 0x02D0 3410 RXCRCERRORS CPSW_STATS Total number of CRC errors frames received 0x02D0 3414 RXALIGNCODEERRORS CPSW_STATS Total number of alignment/code errors received 0x02D0 3418 RXOVERSIZEDFRAMES CPSW_STATS Total number of oversized frames received 0x02D0 341C RXJABBERFRAMES CPSW_STATS Total number of jabber frames received 0x02D0 3420 RXUNDERSIZEDFRAMES CPSW_STATS Total number of undersized frames received 0x02D0 3424 RXFRAGMENTS CPSW_STATS RxFragments received 0x02D0 3428 reserved 0x02D0 342C reserved 0x02D0 3430 RXOCTETS CPSW_STATS Total number of received bytes in good frames 0x02D0 3434 TXGOODFRAMES CPSW_STATS GoodTxFrames 0x02D0 3438 TXBROADCASTFRAMES CPSW_STATS BroadcastTxFrames 0x02D0 343C TXMULTICASTFRAMES CPSW_STATS MulticastTxFrames 0x02D0 3440 TXPAUSEFRAMES CPSW_STATS PauseTxFrames 0x02D0 3444 TXDEFERREDFRAMES CPSW_STATS Deferred Frames 0x02D0 3448 TXCOLLISIONFRAMES CPSW_STATS Collisions 0x02D0 344C TXSINGLECOLLFRAMES CPSW_STATS SingleCollisionTxFrames 0x02D0 3450 TXMULTCOLLFRAMES CPSW_STATS MultipleCollisionTxFrames 168 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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