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TNETV2685FIBZUT7 数据表(PDF) 177 Page - Texas Instruments

部件名 TNETV2685FIBZUT7
功能描述  Digital Media Processor
PDF  191 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2685FIBZUT7 数据表(HTML) 177 Page - Texas Instruments

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VCLK
VTXD[3:0]
VRXD[3:0]
1
2
3
4
Data
Data
TMS320DM647
TMS320DM648
www.ti.com
SPRS372H – MAY 2007 – REVISED APRIL 2012
Table 6-93. Switching Characteristics
Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-54)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
1
td(VCLKH-TXDI)
Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode]
2.25
ns
1
td(VCLKH-TXDI)
Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode]
0.86
ns
2
td(VCLKH-TXDV)
Delay time, VCLK to VTXD[3:0] valid
6.85
ns
Table 6-94. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-54)
720, 800, 900, 1100
NO.
UNIT
MIN
MAX
RTM disabled
0.2
ns
RTM enabled, RXD Flop = 0
1.25
ns
RTM enabled, RXD Flop = 1
0.91
ns
RTM enabled, RXD Flop = 2
0.64
ns
Setup time, VRXD[3:0] valid before VCLK
3
tsu(RXDV-VCLKH)
RTM enabled, RXD Flop = 3
0.36
ns
high
RTM enabled, RXD Flop = 4
0.09
ns
RTM enabled, RXD Flop = 5
-0.18
ns
RTM enabled, RXD Flop = 6
-0.44
ns
RTM enabled, RXD Flop = 7
-0.69
ns
RTM disabled
2
ns
RTM enabled, RXD Flop = 0
0.95
ns
RTM enabled, RXD Flop = 1
1.33
ns
RTM enabled, RXD Flop = 2
1.72
ns
4
th(VCLKH-RXDV)
Hold time, VRXD[3:0] valid after VCLK high
RTM enabled, RXD Flop = 3
2.15
ns
RTM enabled, RXD Flop = 4
2.58
ns
RTM enabled, RXD Flop = 5
3.03
ns
RTM enabled, RXD Flop = 6
3.46
ns
RTM enabled, RXD Flop = 7
3.89
ns
Figure 6-54. VLYNQ Transmit/Receive Timing
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
177
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Product Folder Link(s): TMS320DM647 TMS320DM648



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